• The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International contributing members...
  • RISC-V (pronounced “risk-five”) is an open standard instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
  • RISC-V is a free and open-source instruction set architecture (ISA) that can be used to design custom microprocessors for various applications.
  • ...experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially Berkeley RISC.
  • ...design that allows software engineers to program code in firmware that is supported across a wide variety of devices that support RISC-V instruction sets.
  • RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.
  • RISC-V was created by the Open Source RISC Consortium, a group of leading technology companies and universities.
  • This led to the rise of RISC-V. Before RISC-V, there were several RISC (Reduced Instruction Set Computer) processors in the market.
  • The RISC-V integration into our products opens modular and customizable solutions to address a wide range of markets and applications.